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Preliminary Technical Data
FEATURES
16-Bit, 1.5 LSB INL, 250 kSPS PulSARTM Differential ADC in MSOP/QFN AD7687
APPLICATION DIAGRAM
0.5 TO 5V 5V
16-bit resolution with no missing codes Throughput: 250 kSPS INL: 0.5 LSB typ, 1.5 LSB max (0.0023 % of FSR) S/(N + D): 95 dB @ 20 kHz THD: -115 dB @ 20 kHz True differential analog input range: VREF 0 V to VREF with VREF up to VDD on both inputs No pipeline delay Single-supply 5V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial interface SPI(R)/QSPITM/Wire/DSP compatible Daisy chain multiple ADCs and BUSY indicator Power dissipation 1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5V/100kSPS, 1.4 W @ 2.5 V/100 SPS Stand-by current: 1 nA 10-lead package: MSOP (MSOP-8 size) and QFN (LFCSP), 3 mm x 3 mm same space as SOT-23 Pin-for-pin compatible with the AD7685, AD7686, and AD7688
VREF 0 IN+ IN- VREF 0
REF VDD VIO SDI
1.8 TO VDD 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS)
AD7687
GND
SCK SDO CNV
Figure 2.
Table 1. MSOP, QFN (LFCSP)/SOT-23 16-Bit PulSAR ADC
Type True Differential Pseudo Differential/Unipolar Unipolar 100 kSPS AD7684 AD7683 AD7680 250 kSPS AD7687 AD7685 AD7694 500 kSPS AD7688 AD7686
GENERAL DESCRIPTION
The AD7687 is a 16-bit, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single 5V power supply, VDD. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. On the CNV rising edge, it samples the voltage difference between IN+ and IN- pins. The voltages on these pins usually swing in opposite phase between 0 V to REF. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Its power scales linearly with throughput.
APPLICATIONS
Battery-powered equipment Data acquisition Instrumentation Medical instruments Process control
1.5 Positive INL = +0.30LSB Negative INL = -0.31LSB
1.0
0.5
0.0
-0.5
-1.0
The SPI compatible serial interface also features the ability, using the SDI input, to daisy chain several ADCs on a single 3wire bus and provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate supply VIO. The AD7687 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from -40C to +85C.
INL (LSB)
-1.5 0 16384 32768 Code 49152 65536
Figure 1. Integral Nonlinearity vs. Code.
Rev Pr I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD7687 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Specifications....................................................................... 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Terminology ...................................................................................... 9 Typical Performance Characteristics ........................................... 10 Circuit Information.................................................................... 13
Preliminary Technical Data
Converter Operation.................................................................. 13 Typical Connection Diagram ................................................... 14 Digital Interface .......................................................................... 18 Application Hints ........................................................................... 25 Layout .......................................................................................... 25 Evaluating the AD7687's Performance .................................... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 27
REVISION HISTORY
5/04--Revision I: Preliminary
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Preliminary Technical Data SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = -40C to +85C, unless otherwise noted. Table 2.
Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error2, TMIN to TMAX Gain Error Temperature Drift Offset Error2, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Signal-to-Noise Intermodulation Distortion4 Conditions Min 16 -VREF -0.1 Typ Max
AD7687
Unit Bits V V dB nA
IN+ - IN- IN+, IN- fIN = 250 kHz Acquisition Phase
+VREF VREF + 0.1 65 1 See the Analog Input section.
16 -1 -1.5 REF = VDD = 5 V
VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V VDD = 5 V 5% VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V Full-Scale Step fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 5 V, -60 dB Input fIN = 20 kHz, VREF = 2.5 V 0 0
0.4 0.4 0.4 2 0.3 TBD TBD 0.3 0.05
+1 +1.5 TBD TBD TBD
Bits LSB1 LSB LSB LSB ppm/C mV mV ppm/C LSB kSPS kSPS s dB3 dB dB dB dB dB dB dB
250 200 1.8 95 TBD -115 -115 95 35 TBD TBD
93 TBD
93 TBD
1 2 3
LSB means least significant bit. With the 5 V input range, one LSB is 152.6 V. See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at -7 dB below full-scale.
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AD7687
Table 3.
Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS -3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current1, 2 Power Dissipation Conditions Min 0.5 250 kSPS, REF = 5 V
Preliminary Technical Data
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = -40C to +85C, unless otherwise noted.
Typ Max VDD + 0.3 50 2 2.5 Unit V A MHz ns
VDD = 5 V
-0.3 0.7 x VIO -1 -1
0.3 x VIO VIO + 0.3 +1 +1
V V A A
ISINK = +500 A ISOURCE = -500 A Specified Performance Specified Performance VDD and VIO = 5 V, 25C VDD = 2.5 V, 100 SPS Throughput VDD = 2.5 V, 100 kSPS Throughput VDD = 2.5 V, 200 kSPS Throughput VDD = 5 V, 100 kSPS Throughput VDD = 5 V, 250 kSPS Throughput TMIN to TMAX
Serial 16 Bits Twos Complement Conversion Results Available Immediately after Completed Conversion 0.4 VIO - 0.3 2.3 2.3 1.8 1 1.4 1.35 2.7 4 5.5 VDD + 0.3 VDD + 0.3 50 2.4 4.8 6 15 +85
V V V V V nA W mW mW mW mW C
TEMPERATURE RANGE3 Specified Performance
-40
1 2
With all digital inputs forced to VIO or GND as required. During acquisition phase. 3 Contact Analog Devices, Inc. for extended temperature range.
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Preliminary Technical Data TIMING SPECIFICATIONS
-40C to +85C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. Table 4. VDD = 4.5 V to 5.5 V1
Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO above 4.5 V VIO above 3 V VIO above 2.7 V VIO above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO above 4.5 V VIO above 3 V VIO above 2.7 V VIO above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO above 4.5 V VIO above 2.7 V VIO above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with BUSY indicator) VIO above 4.5 V VIO above 2.3 V Symbol tCONV tACQ tCYC tCNVH tSCK tSCK Min 0.5 1.8 4 10 15 19 20 21 22 7 7 5 14 15 16 17 tEN 15 18 22 25 15 0 5 5 5 4 15 26 Typ
AD7687
Max 2.2
Unit s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSCKL tSCKH tHSDO tDSDO
tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI
1
See Figure 3 and Figure 4 for load conditions.
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AD7687
Preliminary Technical Data
-40C to +85C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. Table 5. VDD = 2.3V to 4.5 V1
Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time between Conversions CNV Pulse Width ( CS Mode ) SCK Period ( CS Mode ) SCK Period ( Chain Mode ) VIO above 3 V VIO above 2.7 V VIO above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO above 3 V VIO above 2.7 V VIO above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO above 2.7 V VIO above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with BUSY indicator) Symbol tCONV tACQ tCYC tCNVH tSCK tSCK Min 0.7 1.8 5 10 25 29 35 40 12 12 5 24 30 35 tEN 18 22 25 30 0 5 8 5 4 TBD ns ns ns ns ns ns ns ns ns ns Typ Max 3.2 Unit s s s ns ns ns ns ns ns ns ns ns ns ns
tSCKL tSCKH tHSDO tDSDO
tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI
1
See Figure 3 and Figure 4 for load conditions.
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Analog Inputs IN+1, IN-1, REF Supply Voltages VDD, VIO to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature JA Thermal Impedance JC Thermal Impedance Lead Temperature Range Vapor Phase (60 sec) Infrared (15 sec) Rating GND - 0.3 V to VDD + 0.3 V or 130 mA -0.3 V to +7 V 7 V -0.3 V to VIO + 0.3 V -0.3 V to VIO + 0.3 V -65C to +150C 150C 200C/W (MSOP-10) 44C/W (MSOP-10) 215C 220C
AD7687
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
See the Analog Input section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
500A
IOL
TO SDO CL 50pF 500A IOH
1.4V
02968-PrH-002
Figure 3. Load Circuit for Digital Interface Timing
70% VIO 30% VIO
tDELAY
2V OR VIO - 0.5V1 0.8V OR 0.5V2
tDELAY
2V OR VIO - 0.5V1 0.8V OR 0.5V2
02968-PrH-003
NOTES 1. 2V IF VIO ABOVE 2.5V, VIO - 0.5V IF VIO BELOW 2.5V. 2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Reference Levels for Timing
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AD7687 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF 1
VDD 2
IN+ 3
IN- 4
GND 5
10
9
Preliminary Technical Data
VIO
SDI
SCK
SDO
CNV
AD7687
8
7
6
Figure 5.10-Lead MSOP and QFN (LFCSP) Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Mnemonic REF VDD IN+ IN- GND CNV Type1 AI P AI AI P DI Function Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 F capacitor. Power Supply. Differential Positive Analog Input. Differential Negative Analog Input. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
7 8 9
SDO SCK SDI
DO DI DI
10
VIO
P
1
AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power
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Preliminary Technical Data TERMINOLOGY
Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (Figure 25). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, i.e., 0 V, from the actual voltage producing the midscale output code, i.e., 0 LSB. Gain Error The first transition (from 100 . . . 00 to 100 . . . 01) should occur at a level 1/2 LSB above the nominal negative full scale (-4.999924 V for the 5 V range). The last transition (from 011...10 to 011...11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (4.999771 V for the 5 V range.) The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the idea levels. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.
AD7687
Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula
ENOB = (S /[N + D ]dB - 1.76 )/ 6.02) and is expressed in bits.
Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB. Aperture Delay Aperture delay is a measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response The time required for the ADC to accurately acquire its input after a full-scale step function was applied.
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AD7687 TYPICAL PERFORMANCE CHARACTERISTICS
1.5 Positive INL = +0.30LSB Negative INL = -0.31LSB 1.5 1.0 1.0
Preliminary Technical Data
Positive DNL = +0.29LSB Negative DNL = -0.31LSB
0.5 DNL (LSB) 0 16384 32768 Code 49152 65536 INL (LSB)
0.5
0.0
0.0
-0.5
-0.5
-1.0
-1.0
-1.5
-1.5 0 16384 32768 Code 49152 65536
Figure 6. Integral Nonlinearity vs. Code
Figure 9. Differential Nonlinearity vs. Code
Figure 7. Histogram of a DC Input at the Code Center
Figure 10. Histogram of a DC Input at the Code Center
Figure 8. FFT Plot
Figure 11. FFT Plot
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Preliminary Technical Data
AD7687
Figure 12. SNR, S/(N + D), and ENOB vs. Reference Voltage
Figure 15. THD, SFDR vs. Reference Voltage
Figure 13. S/[N + D] vs. Frequency
Figure 16. THD vs. Frequency
Figure 14. SNR vs. Temperature
Figure 17. THD, SFDR vs. Temperature
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AD7687
Preliminary Technical Data
Figure 18. SNR and THD vs. Input Level
Figure 21. Operating Currents vs. Temperature
Figure 19. Operating Currents vs. Supply
Figure 22. Offset and Gain Error vs. Temperature
Figure 20. Power-Down Currents vs. Temperature
Figure 23. tDSDO vs. Capacitance Load and Supply
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Preliminary Technical Data
IN+
AD7687
SWITCHES CONTROL MSB REF GND 32,768C 16,384C MSB 4C 2C C C LSB SW-
02968-PrH-005
LSB 4C 2C C C
SW+ BUSY COMP CONTROL LOGIC OUTPUT CODE
32,768C 16,384C
CNV
IN-
Figure 24. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7687 is a fast, low power, single-supply, precise 16-bit ADC using a successive approximation architecture. The AD7687 is capable of converting 250,000 samples per second (250 kSPS) and powers down between conversions. When operating at 100 SPS, for example, it consumes typically 1.4W, ideal for battery-powered applications. The AD7687 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7687 is specified from 2.3 V to 5.5 V, and can be interfaced to either 5 V, 3.3 V, 2.5 V, or 1.8 V digital logic. It is housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines space savings and allows flexible configurations. It is pin-for-pin-compatible with the AD7685, AD7686, and AD7688.
CONVERTER OPERATION
The AD7687 is a successive approximation ADC based on a charge redistribution DAC. Figure 24 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator's input are connected to GND via SW+ and SW-. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN- inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW- are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN- captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536). The control logic toggles these switches, starting with the MSB, in order to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code and a BUSY signal indicator. Because the AD7687 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.
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AD7687
Transfer Functions
The ideal transfer characteristic for the AD7687 is shown in Figure 25 and Table 8.
Preliminary Technical Data
TYPICAL CONNECTION DIAGRAM
Figure 26 shows an example of the recommended connection diagram for the AD7687 when multiple supplies are available.
ADC CODE (TWOS COMPLEMENT)
011...111 011...110 011...101
100...010 100...001
02973-PrH-006
100...000 -FS
-FS + 1 LSB
-FS + 0.5 LSB
+FS - 1 LSB +FS - 1.5 LSB
ANALOG INPUT
Figure 25. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description FSR - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR Analog Input VREF = 5 V 4.999847 V 152.6 V 0V -152.6 V -4.999847 V -5 V Digital Output Code Hexa 7FFF1 0001 0000 FFFF 8001 80002
1
This is also the code for an overranged analog input (VIN+ - VIN above VREF - VGND). 2 This is also the code for an underranged analog input (VIN+ - VIN below -VREF + VGND).
(NOTE 1) 7V REF 10F (NOTE 2) 7V 33 0 TO VREF (NOTE 3) -2V 7V 2.7nF (NOTE 4) IN- 33 VREF TO 0V (NOTE 3) -2V 2.7nF (NOTE 4) NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION. NOTE 2: CREF IS USUALLY A 10F CERAMIC CAPACITOR (X5R). NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION. NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION. NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE. GND REF IN+ VDD VIO SDI SCK SDO CNV 3- OR 4-WIRE INTERFACE (NOTE 5) 100nF 100nF 1.8V TO VDD 5V
AD7687
Figure 26. Typical Application Diagram with multiple supplies
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Preliminary Technical Data
Analog Input
AD7687
During the acquisition phase, the impedance of the analog inputs IN+ and IN- can be modeled as a parallel combination of capacitor C1 and the network formed by the series connection of R1 and C2. C1 is primarily the pin capacitance. R1 is typically 3 k and is a lumped component made up of some serial resistors and the on resistance of the switches. C2 is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to C1. R1 and C2 make a 1-pole, low-pass filter that reduces undesirable aliasing effect and limits the noise. When the source impedance of the driving circuit is low, the AD7687 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency, as shown in Figure 29.
Figure 27 shows an equivalent circuit of the input structure of the AD7687. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN-. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this will cause these diodes to become forward-biased and start conducting current. However, these diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the input buffer's (U1) supplies are different from VDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part.
VDD D1 CPIN GND D2 CIN
IN+ OR IN-
RIN
Figure 27. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the true differential signal between IN+ and IN-. By using these differential inputs, signals common to both inputs are rejected, as shown in Figure 28, which represents the typical CMRR over frequency.
Figure 29. THD vs. Analog Input Frequency and Source Resistance
Figure 28. Analog Input CMRR vs. Frequency
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AD7687
Driver Amplifier Choice
Although the AD7687 is easy to drive, the driver amplifier needs to meet the following requirements:
*
Amplifier AD8021 AD8022 OP184 AD8605, AD8615 AD8519 AD8031
Preliminary Technical Data
Table 9. Recommended Driver Amplifiers.
Typical Application Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single-supply, low power Small, low power and low frequency High frequency and low power
The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7687. Note that the AD7687 has a noise much lower than most of the other 16bit ADCs and, therefore, can be driven by a noisier op amp while preserving the same or better system performance. The noise coming from the driver is filtered by the AD7687 analog input circuit 1-pole, low-pass filter made by R1 and C2 or by the external filter, if one is used. Because the typical noise of the AD7687 is 63 V rms, the SNR degradation due to the amplifier is
Single-to-Differential Driver
For applications using a single-ended analog signal, either bipolar or unipolar, a single-ended-to-differential driver will allow for a differential input into the part. The schematic is shown in Figure 30. When provided a single-ended input signal, this configuration will produce a differential VREF with midscale at VREF/2.
ANALOG INPUT (+/-10V, +/-5V, ..) U1 VREF 100nF 590 VREF 10F 590
SNRLOSS
63 = 20log 2 2 63 + f -3dB ( 2 NeN ) 2

where: f-3dB is the input bandwidth in MHz of the AD7687 (2 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise factor of each amplifiers (+1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/Hz.
*
IN+
590
REF
AD7687
IN-
10k VREF 10k
U2 100nF
Figure 30. Single-Ended-to-Differential Driver Circuit
Voltage Reference Input
The AD7687 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins as explained in the Layout section. When REF is driven by a very low impedance source, e.g., a reference buffer using the AD8031 or the AD8605, a 10 F (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 F (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, smaller reference decoupling capacitor values down to 2.2 F can be used with a minimal impact on performance, especially DNL.
For ac applications, the driver needs to have a THD performance suitable to that of the AD7687. Figure 16 gives the THD versus frequency that the driver should exceed. For multichannel multiplexed applications, the driver amplifier and the AD7687 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16bit level (0.0015%). In the amplifier's data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.
*
Rev Pr I | Page 16 of 28
Preliminary Technical Data
Power Supply
The AD7687 is specified over a wide operating range from 2.3 V to 5.5 V. It has, unlike other low voltage converters, a noise low enough to design a 16-bit resolution system with low supply and with respectable performance. It uses two power supply pins: a core supply VDD and a digital input/output interface supply VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD can be tied together. The AD7687 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 31, which represents PSRR over frequency.
AD7687
Supplying the ADC from the Reference
For simplified applications, the AD7687, with its low operating current, can be supplied directly using the reference circuit, as shown in Figure 33. The reference line can be driven by either:
* * *
The system power supply directly A reference voltage with enough current output capability, such as the ADR43x A reference buffer, such as the AD8031, that can also filter the system power supply, as shown in Figure 33.
5V
5V 10
5V
10k 1F
AD8031
(NOTE 1)
10F
1F
REF
VDD
VIO
AD7687
NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER
Figure 33. Example of Application Circuit Figure 31. PSRR vs. Frequency
The AD7687 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate as shown in see Figure 32. This makes the part ideal for low sampling rate (even a few Hz) and low batterypowered applications.
Figure 32. Operating Currents vs. Sampling Rate
Rev Pr I | Page 17 of 28
AD7687
DIGITAL INTERFACE
Though the AD7687 has a reduced number of pins, it offers flexibility in its serial interface modes. The AD7687, when in CS mode, is compatible with SPI, QSPI, digital hosts, and DSPs, e.g., Blackfin(R) ADSP-BF53x or ADSP219x). This interface can use either 3-wire or 4-wire. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. The AD7687, when in chain mode, provides a daisy chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. In either mode, the AD7687 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a BUSY indicator, the user must time out the maximum conversion time prior to readback. The BUSY indicator feature is enabled as follows:
* In the CS mode, if CNV or SDI is low when the ADC conversion ends (Figure 37 and Figure 41). * In the chain mode, if SCK is high during the CNV rising edge (Figure 45).
Preliminary Technical Data
Rev Pr I | Page 18 of 28
Preliminary Technical Data
CS MODE 3-Wire, No BUSY Indicator
This mode is usually used when a single AD7687 is connected to an SPI compatible digital host. The connection diagram is shown in Figure 34 and the corresponding timing is given in Figure 35. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. Once a conversion is initiated, it will continue to completion irrespective of the state of CNV. For instance, it could be useful to bring CNV low to select other SPI devices, such as analog multiplexers, but CNV must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7687 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are
AD7687
then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance.
CONVERT CNV VIO SDI DIGITAL HOST SDO DATA IN
AD7687
SCK
CLK
Figure 34. CS Mode 3-Wire, No BUSY Indicator Connection Diagram (SDI High)
SDI = 1
tCYC tCNVH
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSCK tSCKL
SCK
1 tHSDO tEN
2
3
14 tSCKH tDSDO
15
16
SDO
D15
D14
D13
D1
D0
Figure 35. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
Rev Pr I | Page 19 of 28
02968-PrH-008
tDIS
AD7687
CS Mode 3-Wire with BUSY Indicator
This mode is usually used when a single AD7687 is connected to an SPI compatible digital host having an interrupt input. The connection diagram is shown in Figure 36 and the corresponding timing is given in Figure 37. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV could be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pullup on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7687 then enters the acquisition phase and powers
Preliminary Technical Data
down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance.
CONVERT CNV VIO SDI VIO 47k SDO DATA IN IRQ CLK DIGITAL HOST
AD7687
SCK
Figure 36. CS Mode 3-Wire with BUSY Indicator Connection Diagram (SDI High)
SDI = 1
tCYC tCNVH
CNV
tCONV ACQUISITION CONVERSION
tACQ ACQUISITION tSCK tSCKL
SCK
1 tHSDO tDSDO
2
3
15 tSCKH
16
17
SDO
D15
D14
D1
D0
Figure 37. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
Rev Pr I | Page 20 of 28
02968-PrH-010
tDIS
Preliminary Technical Data
CS Mode 4-Wire, No BUSY Indicator
This mode is usually used when multiple AD7687s are connected to an SPI compatible digital host. A connection diagram example using two AD7687s is shown in Figure 38 and the corresponding timing is given in Figure 39. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers,
AD7687
but SDI must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7687 enters the acquisition phase and powers down. Each ADC result can be read by bringing low its SDI input which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK driving edges. The data is valid on both SCK edges. Although the nondriving edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge, or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7687 can be read.
CS2 CS1 CONVERT CNV SDI CNV SDO SDI DIGITAL HOST SDO
AD7687
SCK
AD7687
SCK
DATA IN CLK
Figure 38. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
tCYC
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK tSCKL
SCK 1 2 3 14 15 16 17 18 30 31 32
tHSDO tEN
SDO D15 D14
tSCKH tDSDO
D13 D1 D0 D15 D14 D1 D0
tDIS
02968-PrH-012
Figure 39. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing
Rev Pr I | Page 21 of 28
AD7687
CS Mode 4-Wire with BUSY Indicator
This mode is usually used when a single AD7687 is connected to an SPI compatible digital host, which has an interrupt input, and it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 40 and the corresponding timing is given in Figure 41. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to
Preliminary Technical Data
low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7687 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK driving edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or SDI going high, whichever is earlier, the SDO returns to high impedance.
CS1 CONVERT CNV SDI VIO 47k SDO DATA IN IRQ CLK DIGITAL HOST
AD7687
SCK
Figure 40. CS Mode 4-Wire with BUSY Indicator Connection Diagram
tCYC
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSSDICNV
SDI
tHSDICNV tSCKL
SCK 1 2 3 15
tSCK
16
17
tHSDO tDSDO tEN
SDO D15 D14
tSCKH
02968-PrH-014
tDIS
D1 D0
Figure 41. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
Rev Pr I | Page 22 of 28
Preliminary Technical Data
Chain Mode, No BUSY Indicator
This mode can be used to daisy chain multiple AD7687s on a 3wire serial interface. This feature is useful for reducing component count and wiring connections, e.g., in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7687s is shown in Figure 42 and the corresponding timing is given in Figure 43. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the BUSY indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output
AD7687
onto SDO and the AD7687 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 x N clocks are required to readback the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate and, consequently more AD7687s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. For instance, with a 5 ns digital host set-up time and 3 V interface, up to five AD7687s running at a conversion rate of 250 kSPS can be daisy-chained on a 3-wire port.
CONVERT CNV SDI CNV SDO SDI DIGITAL HOST SDO DATA IN
AD7687
A SCK
AD7687
B SCK
CLK
Figure 42. Chain Mode, No BUSY Indicator Connection Diagram
SDIA = 0
tCYC
CNV tCONV ACQUISITION CONVERSION
tACQ
ACQUISITION
tSSCKCNV
SCK 1 2 3
tSCKL
14 15
tSCK
16 17 18 30 31 32
tHSCKCNV tEN
SDOA = SDIB
tSSDISCK tHSDISC
DA15 DA14 DA13 DA1
tSCKH
DA0
SDOB
DB15
DB14
DB13
DB1
DB0
DA15
DA14
DA1
DA0
Figure 43. Chain Mode, No BUSY Indicator Serial Interface Timing
Rev Pr I | Page 23 of 28
02968-PrH-016
tHSDO tDSDO
AD7687
Chain Mode with BUSY Indicator
This mode can also be used to daisy chain multiple AD7687s on a 3-wire serial interface while providing a BUSY indicator. This feature is useful for reducing component count and wiring connections, e.g., in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7687s is shown in Figure 44 and the corresponding timing is given in Figure 45. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the BUSY indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the nearend ADC ( ADC C in
Preliminary Technical Data
Figure 44) SDO will be driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host. The AD7687 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are then clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 x N + 1 clocks are required to readback the N ADCs. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate and, consequently more AD7687s in the chain, provided the digital host has an acceptable hold time. For instance, with a 5 ns digital host set-up time and 3 V interface, up to five AD7687s running at a conversion rate of 250 kSPS can be daisy-chained to a single 3-wire port.
CONVERT CNV SDI CNV SDO SDI CNV SDO SDI DIGITAL HOST SDO DATA IN IRQ CLK
AD7687
A SCK
AD7687
B SCK
AD7687
C SCK
Figure 44. Chain Mode with BUSY Indicator Connection Diagram
tCYC
CNV = SDIA
tCONV
CONVERSION
tACQ
ACQUISITION
ACQUISITION
tSSCKCNV
SCK 1 2 3
tSCKH
4
tSCK
15 16 17 18 19 31 32 33 34 35 47 48 49
tHSCKCNV
SDOA = SDIB
tEN
tSSDISCK
tHSDISC
DA1
tSCKL
DA0
DA15 DA14 DA13
tHSDO tDSDO
SDOB = SDIC DB15 DB14 DB13 DB1 DC1 DB0 DA15 DA14 DC0 DB15 DB14 DA1 DB1 DA0 DB0 DA15 DA14 DA1 DA0
02968-PrH-018
tDSDOSDI
SDOC DC15 DC14 DC13
Figure 45. Chain Mode with BUSY Indicator Serial Interface Timing
Rev Pr I | Page 24 of 28
Preliminary Technical Data APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7687 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7687 with all its analog signals on the left side and all its digital signals on the right side eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7687 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided At least one ground plane should be used. It could be common or split between the digital and analog section. In such a case, it should be joined underneath the AD7687s. The AD7687 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. That is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and connect these pins with wide, low impedance traces. Finally, the power supply VDD and VIO of the AD7687 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7687 and connected using short and large traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. An example of layout following these rules is shown in Figure 46 and Figure 47.
AD7687
Figure 46. Example of Layout of the AD7687 (Top Layer)
EVALUATING THE AD7687'S PERFORMANCE
Other recommended layouts for the AD7687 are outlined in the evaluation board for the AD7687 (EVAL-AD7687). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD2.
Figure 47. Example of Layout of the AD7687 (Bottom Layer)
Rev Pr I | Page 25 of 28
AD7687 OUTLINE DIMENSIONS
3.00 BSC
Preliminary Technical Data
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA 1.10 MAX 8 0 0.80 0.60 0.40
SEATING PLANE
0.23 0.08
Figure 48.10-Lead Micro Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
INDEX AREA
3.00 BSC SQ
1
0.50 BSC
0.50 0.40 0.30 1.74 1.64 1.49
1.50 BCS SQ
TOP VIEW
5
PIN 1 INDICATOR
EXPOSED PAD
(BOTTOM VIEW)
10
6
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
2.48 2.38 2.23
PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES
Figure 49. 10-Lead Lead Frame Chip Scale Package [ QFN (LFCSP)] 3 mm x 3 mm Body (CP-10) Dimensions shown in millimeters
Rev Pr I | Page 26 of 28
Preliminary Technical Data
ORDERING GUIDE
Models AD7687BRM AD7687BRMRL7 AD7687BCPWP AD7687BCPRL7 EVAL-AD7687CB1 EVAL-CONTROL BRD22 EVAL-CONTROL BRD32 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package (Option) MSOP (RM-10) MSOP (RM-10) QFN [LFCSP] (CP-10) QFN [LFCSP] (CP-10) Evaluation Board Controller Board Controller Board Transport Media, Quantity Tube, 50 Reel, 1,000 Waffle pack, 50 Reel, 1,500
AD7687
Brand C03 C03 C03 C03
1 2
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Rev Pr I | Page 27 of 28
AD7687 NOTES
Preliminary Technical Data
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR02972-0-5/04(PrI)
Rev Pr I | Page 28 of 28
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